1. Field of the Invention
The present invention is related to a magnetic field detecting apparatus for intermittently detecting a magnetic field, and also, related to an electronic appliance containing the above-described magnetic field detecting apparatus.
2. Description of the Related Art
As one of magnetic field detecting apparatuses, Hall ICs utilizing Hall-effect elements have been proposed. Also, among these Hall ICs, there are some Hall ICs equipped with intermittent driving functions in order to achieve low power consumption (refer to non-patent publication 1).
FIG. 16 is a block diagram for showing a Hall IC 10 equipped with an intermittent driving function. As shown in FIG. 16, the Hall IC 10 is provided with a power supply terminal 11, a GND terminal 13, an output terminal 15, an oscillator 101, a control logic circuit 103, a magnetic field detecting circuit 105, and an output inverter circuit 113. In the output inverter circuit 113, an NMOS 109 and a PMOS 111 have been series-connected to each other. A gate of the NMOS 109 and a gate of the PMOS 111 have been commonly connected to each other so as to constitute a common gate, and an output of the magnetic field detecting circuit 105 has been connected to the common gate An output terminal 15 has been connected to a common drain of the NMOS 109 and the PMOS 111.
FIG. 17(a) is a diagram for showing magnetic flux density “B” of a peripheral portion of the Hall IC 10; FIG. 17(b) is a diagram for representing a clock signal outputted from the oscillator 101; FIG. 17(c) is a diagram for indicating an output signal of a control logic circuit 103; and FIG. 17(d) is a diagram for showing an output signal outputted from the output terminal 15. Referring now to FIG. 16 and FIG. 17, a description is made of respective structural elements provided in the Hall IC 10 shown in FIG. 16.
The oscillator 101 outputs the clock signal having a constant time period “Tclk” represented in FIG. 17(b). The control logic circuit 103 frequency-divides the above-described clock signal, and then, performs a logic synthesizing operation with respect to the frequency-divided clock signals so as to output a signal having a constant time period “Ts” shown in FIG. 17(c). This time period “Ts” of the output signal is “n” times longer than the time period “Tclk” of the clock signal, while a time “Ton” of an H level and a time “Toff” of an L level are contained in 1 time period. The time “Ton” is very short with respect to 1 time period, whereas a major portion of 1 time period is the time “Toff.”
The above-described signal outputted from the control logic circuit 103 is supplied to the magnetic field detecting circuit 105. The magnetic field detecting circuit 105 is energized in response to a signal supplied from the control logic circuit 103, namely, is energized during the time “Ton”, and is not energized during the time “Toff.” As a consequence, the magnetic field detecting circuit 105 performs an intermittent driving operation. As a result, low power consumption of the magnetic field detecting circuit 105 may be realized.
The magnetic field detecting circuit 105 contains a Hall-effect element 121, an amplifier 123, a comparator having a hysteresis characteristic (will be referred to as “hysteresis comparator” hereinafter) 125, and a latch circuit 127. The Hall-effect element 121 outputs a Hall-effect voltage in response to the magnetic flux density “B” (otherwise, magnetic field) around this Hall-effect element 121. The amplifier 123 amplifies the Hall voltage outputted from the Hall-effect element 121, and then, inputs the amplified Hall voltage to the hysteresis comparator 125.
The hysteresis comparator 125 compares the amplified Hall voltage with a reference voltage, and then, outputs a signal having such a level in response to high/low relationship between the amplified Hall voltage and the reference voltage, and the hysteresis. Namely, the hysteresis comparator 125 outputs a signal having an H level, or a signal having an L level.
The latch circuit 127 latches an output signal of the hysteresis comparator 125 obtained in the above-described time “Ton” during the above-described time “Toff.” An output voltage of the latch circuit 127 is applied to the common gate of the output inverter circuit 113.
In response to the magnetic flux density “B”, either a signal having an “H”-level voltage or a signal having an “L”-level voltage is outputted from the output terminal 15. For instance, in such a case that magnetic flux density around the Hall-effect element 121 is such a magnetic flux density “B” indicated in FIG. 17(a), such a signal having the voltage level represented in FIG. 17(d) is outputted from the output terminal 15.
Non-patent Publication 1: “Product Catalog for Hall IC series Application Notebook” issued from Handotai-Sha, Matsushita Electric Company, in 2004
In accordance with the above-explained Hall IC 10, since the magnetic field (magnetic flux density “B”) is detected in the intermittent manner, the low power consumption thereof can be realized. However, the investigation of the Hall IC can be prolonged. In other words, as shown in FIG. 17(c), the detecting operation of the magnetic field is carried out only for the times “Ton” in an interval of the time period “Ts”. As a consequence, when the investigating operation is performed during which the magnetic field is detected plural times, both the Hall IC 10 and the investigating apparatus are brought into waiting statuses for the times “Toff.” As a result, the investigation time per a single piece of the Hall IC 10 is prolonged.
In order to shorten an investigation time of a Hall IC, the below-mentioned method for adding a test mode may be conceived. In this test mode, both the time “Toff” and the time period “Ts” represented in FIG. 17(c) are made shorter than those of the normal mode. However, due to such a reason that the above-described Hall IC is a miniature chip and the miniature Hall IC has no input pin for a mode selection purpose, the test mode can be very hardly added and set.